The present invention relates generally to integrated circuit packaging devices, and, more particularly, to an apparatus and method for providing bypass capacitance and power routing in a quad flat pack (QFP) package.
As is generally known in the art, an integrated circuit (IC) is formed on a small, substantially planar, piece of semiconductor material (e.g., silicon) referred to as a chip or integrated circuit die. A typical integrated circuit die includes a vast number of circuits therein and also features a plurality of bonding pads disposed on its top surface adjacent its peripheral edges. In a conventional quad flat pack (QFP) package assembly 100 such as shown in FIG. 1, the integrated circuit die 102 is mounted directly to a centrally located die paddle 104, which is part of a thin metal lead frame 106 that is typically stamped or chemically etched from strips of copper-containing containing materials. The die paddle is generally rectangular in shape and is supported at each of its four corners by a radially extending support beam 108.
The lead frame 106 further includes a plurality of thin, closely spaced conductive leads 110 whose inner ends radially extend away from the edges of the die 102. The inner ends of the conductive leads are also referred to as bonding fingers. Very small diameter gold bonding-wires 112 have one end thereof bonded to the corresponding bonding pads on the integrated-circuit die 102, and the other end thereof bonded to the corresponding bonding fingers 110. The entire assembly thus described may be encapsulated in a molded plastic material so as to form a molded-plastic package body.
Integrated circuits (including those mounted in QFP assemblies) typically include active circuits that can draw spikes of current from a local power supply line or bus. One example of an active circuit that may draw such a spike of current is a digital logic element disposed on an integrated circuit. The digital logic element has a VCC power lead that is coupled by a power (VCC) bus network within the IC to the power VCC pads of the integrated circuit. Furthermore, the VCC pads of the IC are connected via bond wires 112 to the bonding fingers 110, and the bonding fingers are connected finally to a PC (printed circuit) board where the VCC supply is provided for the packaged IC. This path for supply current can be quite long and may have significant resistance and inductance associated therewith. When a signal on an input lead of the digital logic element switches from one digital logic level to another digital logic level, the digital logic element may draw a spike of current from the power supply line. This spike of current can include a crossover current that passes from the VCC power lead of the digital logic element through the digital logic element and to a ground lead of the digital logic element, or could also include a switching current needed to supply electrical charge to the load of the digital logic element such that the voltage on the output of the digital logic element can transition from one digital logic voltage to another.
Ideally, if the supply current path had no resistance or inductance, then the spike of current could be supplied to the digital logic element through the supply line without a significant drop in the voltage on the VCC power lead of the digital logic element. However, because some resistance and inductance is inherently associated with the power supply path, the voltage on the VCC power lead of the digital logic element may drop momentarily when the digital logic element switches from one digital logic level to another. Such a voltage drop can have undesirable consequences. For example, where the signal output from the digital logic element is to switch from a digital logic low to a digital logic high, the voltage on the VCC power lead of the as a digital logic element might momentarily dip to a level that is not recognized as a digital logic high. This voltage dip can delay the transition of the signal and can cause other problems.
Accordingly, one technique used to prevent undesirable dips in supply voltage to active devices is to provide bypass capacitors for the active devices. When an active device draws a spike of current, much of this current is supplied by a bypass capacitor, thereby reducing the magnitude of the current spike pulled through the VCC power supply line. By reducing the magnitude of the current spike conducted through the supply line, the magnitude of the associated voltage drop at the power supply lead of the active device is reduced as well. Conventionally, such bypass capacitors are located outside the QFP package on a printed circuit board. The inductance and resistance of the supply path reduce the effectiveness of a bypass capacitor from the capacitor to the supply lead of the logic element. This location suffers from the inductance and resistance of the leadframe, bondwire, and on-die power supply path that stands between the capacitor and a logic element disposed on an IC. Although this situation may be improved by locating discrete bypass capacitors within the QFP package, they are quite bulky and difficult to interconnect. Even inside the QFP package, these bypass capacitors still suffer some resistive and inductive losses due to their individual packaging and conductive interconnects to the IC.